Method and apparatus for scrambling read data in a memory module

ABSTRACT

Provided are a method and apparatus method and apparatus for scrambling read data in a memory module. A read data packet having scrambled read data returned in response to a read request is received. The scrambler seed is updated in response to receiving the read data packet. The scrambler seed is used to descramble the scrambled read data.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.13/977,653, filed Jun. 28, 2013, which is the National Stage ofInternational Application No. PCT/US2013/032633, filed Mar. 15, 2013,wherein all the above related applications are all incorporated hereinby reference in their entirety.

TECHNICAL FIELD

Embodiments described herein generally relate to a memory system inwhich a host memory controller communicates on a single channel or buswith multiple memory modules that have a pin layout compatible with theslots coupled to the channel and host memory controller. The host memorycontroller supports a protocol used by the multiple memory modulescoupled to the channel, such as the Double Data Rate Third Generation(DDR3) protocol. If memory modules, such as Dual In-Line Memory Modules(DIMMs), have different timings for outputting data on the bus, such asthe case with different types of DIMMs, then the host memory controllerhas to adjust for those timing differences among the different coupledDIMMs. The host memory controller may communicate single cycle commands.

Before using the bus, the host memory controller must configure thememory modules for operations. In the DDR3 protocol, the host memorycontroller may use a Mode Register Set (MRS) command to program up toeight mode registers in the memory chips, such as Dynamic Random AccessMemory (DRAM) chips, on the memory module package. The MRS commandidentifies the mode register on the memory chip and includes aninversion bit indicating whether data is inverted. After the bus istrained, the host memory controller may then use the bus for read andwrite commands and to transfer data.

Commands may be sent one bit per lane per command. During a normaltiming mode, e.g., 1N timing, the chip select signal is placed on thebus on the cycle of the command to cause the selected memory module toaccept the command. During high speed operations, such as during 2Ntiming, the host memory controller places the chip select signal on thebus one clock cycle before the command to allow for additional setuptime.

A clock enable signal may be used to manage internal clock signals inthe memory module. A clock enable (CKE) high signal activates internalclock signals and is maintained high throughout read and write accesses.A CKE low signal to the memory module deactivates internal clocksignals, device input buffers and output drivers. Taking CKE Low signalspower down and refresh operations.

When writes are communicated from the host memory controller to a memorymodule, the writes at the memory module may be directly written to thememory chips. However, in memory modules having a write buffer, a creditsystem may be implemented where the host memory controller is allotted amaximum number of write credits and cannot send a write command unlessthere are available write credits. The write credits are decrementedupon sending a write command. The memory module will send a message overthe bus when each write has completed to return the credit to the hostmemory controller, which increments the write credit counter when themessage is received.

To avoid communicating a vexatious pattern when sending read and writerequests, current host memory controllers may scramble the data toreduce the probability of repeatedly producing a vexatious pattern thatcan cause an error on the bus. Upon receiving scrambled write data witha write address, the memory module stores the scrambled write data atthe write address. In response to a read request, the scrambled datathat is stored and sent over the bus to the host memory controller todescramble and use.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are described by way of example, with reference to theaccompanying drawings, which are not drawn to scale, in which likereference numerals refer to similar elements.

FIG. 1 illustrates an embodiment of a system having a memory system.

FIG. 2 illustrates an embodiment of a memory module.

FIG. 3 illustrates an embodiment of a pin-out design of the memorysystem.

FIG. 4 is an embodiment of operations to generate and process a requestsignal encoding a function.

FIG. 5 illustrates an embodiment of operations go determine a timingadjustment for output in a memory module.

FIG. 6 illustrates an embodiment of a mode register set (MRS) command.

FIG. 7 illustrates an embodiment of operations for generating andprocessing the MRS command.

FIGS. 8 and 9 provide timing charts for outputting a command in twoparts.

FIGS. 10 and 11 illustrate embodiments of operations for generating andaccepting a command sent on multiple clock cycles.

FIG. 12 illustrates an embodiment of operations to indicate a supportedinterface configuration to the memory module controller.

FIG. 13 illustrates an embodiment of operations for the memory modulecontroller to use address bits based on a supported interfaceconfiguration.

FIG. 14 illustrates an embodiment of operations to use commands toindicate power management operations.

FIG. 15 illustrates an embodiment of operations to use write credits tosend write commands and return write credits to the host memorycontroller.

FIG. 16 illustrates an embodiment of operations to generate a read datapacket with a write credit counter.

FIG. 17 illustrates an embodiment of operations to process a read datapacket.

FIG. 18 illustrates an embodiment of operations to process a flow oferror operations using an error signal.

FIG. 19 illustrates an embodiment of operations to process a writeerror.

FIG. 20 illustrates an embodiment of operations to scramble anddescramble data transmitted over the bus.

FIG. 21 illustrates an embodiment of operations to descramble write datain the memory module.

FIG. 22 illustrates an embodiment of operations to set a parameterindicting a bus interface configuration.

FIG. 23 illustrates an embodiment of operation to select a bus interfaceconfiguration to process a transfer request.

DESCRIPTION OF EMBODIMENTS

In the following description, numerous specific details such as logicimplementations, opcodes, means to specify operands, resourcepartitioning/sharing/duplication implementations, types andinterrelationships of system components, and logicpartitioning/integration choices are set forth in order to provide amore thorough understanding of the present invention. It will beappreciated, however, by one skilled in the art that the invention maybe practiced without such specific details.

In other instances, control structures, gate level circuits and fullsoftware instruction sequences have not been shown in detail in ordernot to obscure the invention. Those of ordinary skill in the art, withthe included descriptions, will be able to implement appropriatefunctionality without undue experimentation.

References in the specification to “one embodiment,” “an embodiment,”“an example embodiment,” etc., indicate that the embodiment describedmay include a particular feature, structure, or characteristic, butevery embodiment may not necessarily include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment.

In the following description and claims, the terms “coupled” and“connected,” along with their derivatives, may be used. It should beunderstood that these terms are not intended as synonyms for each other.“Coupled” is used to indicate that two or more elements, which may ormay not be in direct physical or electrical contact with each other,co-operate or interact with each other. “Connected” is used to indicatethe establishment of communication between two or more elements that arecoupled with each other. Certain embodiments relate to memory deviceselectronic assemblies. Embodiments include both devices and methods forforming electronic assemblies.

FIG. 1 illustrates an embodiment of a computing system 2 including oneor more processors 4, a host memory controller 6 and multiple memorymodules 8 a, 8 b, which are typically mounted on a motherboard. Theprocessors 4 may comprise a central processing unit, multi-coreprocessor. The host memory controller 6, in response to memory accessrequests from the processors 4, communicates with multiple memorymodules 8 a, 8 b over a bus 10, also referred to as a channel, businterface, etc., where both memory modules 8 a, 8 b are separately andindependently connected to the same bus 10. The host memory controller 6may include a request counter 7 that is incremented when receiving arequest signal for a grant to use when later issuing grants based on thenumber of requests indicated in the request counter 7, a write creditcounter 9 indicating a number or credits permitting write requests to besent to one of the memory modules 8 a, 8 b, and a scramble seed value 11used to descramble read requested data from one of the memory modules 8a, 8 b.

In the embodiment of FIG. 1, the memory modules 8 a, 8 b are mounted inslots or memory sockets on the system 2 motherboard. The memory modules8 a, 8 b may comprise the same or different types of memory modules thathave a pin arrangement compatible with the pin arrangement in the memoryslots on the motherboard. Further, the memory modules may support thesame or different memory protocols, such as Double Data Rate FourthGeneration (DDR4) protocol and additional protocols. Although only twomemory modules 8 a, 8 b are shown, there may be multiple memory modules

Each of the memory modules 8 a, 8 b include memory chips 12 a, 14 a, 16a, 18 a and 12 b, 14 b, 16 b, 18 b, respectively, on one or both sidesof the memory module, to store the data. The memory chips, e.g., DRAMchips, located on one or both sides of the memory module 8 a, 8 bpackage, comprise the storage elements that store data being used by theprocessor 4.

Each memory module 8 a, 8 b may include a memory module controller 20 a,20 b to coordinate memory management and access operations with the hostmemory controller 6. The host memory controller 6 includes logic tomanage read and write operations and memory management operations withrespect to the memory modules 8 a, 8 b connected to the bus 10, andinterface the processor 4 to the memory modules 8 a, 8 b. The hostmemory controller 6 may be integrated with the processor 4 orimplemented in logic separate from the processor 4 on the system 2motherboard.

The system 2 motherboard may include a memory socket compatible withdifferent types of memory chips, to allow different types of memorymodules 8 a, 8 b supporting different types of memory devices supportingdifferent memory protocols as long as the different types of memorymodules 8 a, 8 b are compatible with the pin architecture in the memorysockets.

In one embodiment, the memory modules 8 a, 8 b may comprise a same ordifferent type of Dynamic Random Access Memories (DRAMs). In oneembodiment, the memory modules 8 a, 8 b may comprise Dual In-Line MemoryModules (DIMMs), such as unbufferred DIMMs (UDIMM), Load ReducedDual-inline Memory Module (LRDIMM), a Small Outline Dual In-line MemoryModule (SODIMM), etc. The memory modules 8 a, 8 b may implement variousforms of memory, including, but not limited to, NAND (flash) memory,ferroelectric random-access memory (FeTRAM), nanowire-based non-volatilememory, three-dimensional (3D) crosspoint memory such as phase changememory (PCM), memory that incorporates memristor technology,Magnetoresistive random-access memory (MRAM), Spin Transfer Torque(STT)-MRAM, etc.

In certain embodiments, because different types of memory modules 8 a, 8b may be mounted and connected to the bus 10, the memory modules 8 a, 8b may support different protocols. For instance, the memory module 8 amay comprise a type of DIMM conforming to the Double Data Rate FourthGeneration (DDR4) Static DRAM (SDRAM) protocol and the memory module 8 bmay use a different protocol but be compatible on the same bus 10 withthe memory module 8 a using the DDR4 protocol. Alternative and differentprotocols may also be used and implemented in the memory modules 8 a, 8b.

If the memory modules 8 a, 8 b support different DRAM protocols, thenthe host memory controller 6 is configured to communicate usingdifferent protocols over the bus 10, a first protocol specific to thememory module 8 a, e.g., DDR4, and a second memory protocol specific tothe memory module 8 b. Read and management requests to the memory module8 a are implemented with the first memory protocol and to the secondmemory module 8 b using the second memory protocol.

FIG. 2 provides further details of an embodiment of a memory module 8,such as the memory modules 8 a, 8 b, as including a memory modulecontroller 20 performing the memory module operations and interactionswith the host memory controller 6. In certain implementations, one ofthe memory modules, e.g., 8 b, may include the memory module of FIG. 2,and the other memory module, e.g., 8 a, may not include the memorymodule controller 20, such as a memory module 8 a conforming to the DDR4standard. In such embodiments, the memory module 8 a, may include aregister, such as the case with a RDIMM or a buffer, such as the casewith a LRDIMM.

The memory module 8 may include mode registers 22 in the memory modulecontroller having data which may be configured using a Mode Register Set(MRS) command, a read buffer 24 to buffer read data being returned tothe host memory controller 6 in response to a read command, a powermanagement operations register 26 indicating power management operationsto perform, a write buffer 28 to buffer write data before being writtento the memory chips 12, 14, 16, 18, a write credit counter 30 indicatinga number of write credits to return to the host memory controller 6, ascramble seed value 32 used to randomize read data transferred over thebus 10 to the host memory controller 6, and an interface parameter 34identifying a supported interface configuration of the bus 10. Thebuffers and parameters 24, 26, 28, 30, 32, and 34 may be implementedwithin the memory module controller 20 or in circuitry external to thememory module controller 20 in the memory module 8. Certain of theparameters 26, 30, 32, and 34 may be implemented in mode registers 22.

In certain embodiments, the memory module 8 a may comprise a near memorythat is configured as a caching layer for a far memory comprising memorymodule 8 b. In such configuration, the near memory module 8 a shouldhave the effect of reducing the access times of the most frequentlyaccessed system memory addresses that the specific far memory module 8 bis designed to cache. The near memory devices may be configured as adirect mapped cache for their far memory counterparts.

The described memory module controller 20 and host memory controller 6embodiments may be encoded in hardware logic, such as in an ApplicationSpecific Integrated Circuit (ASIC), Field Programmable Gate Array(FPGA), etc.

Elements of embodiments of the present invention may also be provided asa machine-readable medium for storing the machine-executableinstructions. The machine-readable medium may include, but is notlimited to, flash memory, optical disks, compact disks-read only memory(CD-ROM), digital versatile/video disks (DVD) ROM, random access memory(RAM), erasable programmable read-only memory (EPROM), electricallyerasable programmable read-only memory (EEPROM), magnetic or opticalcards, propagation media or other type of machine-readable mediasuitable for storing electronic instructions. For example, embodimentsof the invention may be downloaded as a computer program which may betransferred from a remote computer (e.g., a server) to a requestingcomputer (e.g., a client) by way of a network transmission.

FIG. 3 illustrates an arrangement of the pins on the memory module 8 a,8 b, with the host memory controller 6, bus 10 lines and the memorymodules 8 a, 8 b, where such pin designations are described below orknown in the art.

Encoding Functions in a Request Signal

In certain embodiments, the memory module controller 20 may send arequest signal, e.g., REQ# 50, to the host memory controller 6 toindicate that there is data in the read buffer 24 for the host memorycontroller 6 to return as part of a read command. The request signal maycomprise the REQ# clock enable (CKE) signal 50 shown in the pin-outdiagram of FIG. 3. The memory module controller 18 may transmit therequest signal at a minimum pulse width to guarantee detection by thehost memory controller 6, which in certain implementations may comprisetwo clock cycles. The memory module controller 20 may further encode anadditional function in the request signal for the host memory controller6 to perform. By encoding additional functions in the request signal,multiple functions may be indicated in one signal in order to maximizethe number of operations and information communicated in a singlesignal.

FIG. 4 illustrates an embodiment of operations performed by the hostmemory controller 6 and memory module controller 20 to use the requestsignal to communicate additional functions to the host memory controller6. Upon initiating (at block 100) an operation to generate a requestsignal, which may be part of a read command to transfer data from theread buffer 24 back to the host memory controller 6, the memory modulecontroller 20 determines (at block 102) a function to include with therequest signal, which function may indicate additional operations forthe host memory controller 6 to perform, such as a specific errorcondition or interrupt or other functions. The memory module controller20 then determines (at block 104) a pulse width used to indicate orencode the determined function. For instance a pulse width equal to theminimum pulse width to guarantee detection by the host memory controller6 of the request signal may be used to indicate or encode a firstfunction, additional pulse widths that are greater than the minimumpulse width may be used to indicate additional functions. For instance,if the minimum pulse width to guarantee detection is two clocks, thenthis minimum pulse width for the request signal may indicate onefunction, and pulse widths of 6, 10, and 14 may indicate yet additionaldifferent functions. A pulse width of 14 may indicate a catastrophicfailure. Further, the different pulse widths for the request signalassociated with different functions may be separated by a minimum numberof clock cycles, such as 3 cycles in certain embodiments, to guaranteeproper detection by the host memory controller 6 of the pulse width. Thememory module controller 20 generates (at block 106) the request signalhaving the determined pulse width to send to the host memory controller6.

Upon detecting (at block 108) the request signal REQ0# on pin 50 havingthe minimum or first pulse width, e.g., 2 clocks, the host memorycontroller 6 increments (at block 110) a request counter 7 indicating anumber of grant signals that need to be sent to the memory module 8 bsending the request signal. After incrementing the request counter 7,the host memory controller 6 may wait until a slot on the bus 10, i.e.,data bus, is available to issue multiple of the grant request, such thatthe requests indicated in the request counter 7 are processed in a batchat different random times. Upon receiving the grant signal, the memorymodule controller 20 sends (at block 112) data in the read buffer 24 tothe host memory controller 6, such as data gathered and buffered inresponse to a read request from the host memory controller 6.

After determining the minimum or first pulse width of the request signal50, if the request signal 50 (at block 114) does not continue beyond themeasured minimum pulse width, then control ends. Otherwise, if (at block116) the measured request signal does not continue beyond a second pulsewidth, e.g., 6 clocks, then the host memory controller 6 may execute (atblock 118) a second function associated with that second pulse width.Otherwise, if (at block 120) the request signal 50 does not continuebeyond a measured third pulse width, e.g., 10 clocks, then the hostmemory controller 6 may execute (at block 122) a third functionassociated with that third pulse width. If the pulse width continues anda fourth pulse width, e.g., 14 clocks, is measured (at block 124), thenthe host memory controller 6 may execute (at block 126) catastrophicfailure handling for the host memory controller 6 to perform.

Although the described embodiments concern four functions for fourdifferent pulse widths of the request signal, in certain implementationsthere may be more or less than four functions represented by more orless than four pulse widths. Further, one pulse width may indicate a setof multiple functions to perform.

In the operations of FIG. 4, the functions beyond the initial requestgrant function are only processed after determining that the pulse widthdoes not continue beyond the pulse width associated with thoseadditional functions. In an alternative embodiment, each additionalfunction may execute upon measuring the pulse width associated with thatfunction even if the pulse width continues beyond that measured pulsewidth, so each function is executed as measurements of the pulse widthextend beyond the trigger pulse width.

With the described embodiment of FIG. 4, different functions may beencoded into a request signal by the memory module controller 20 byusing different pulse widths for the memory module controller that maybe separated by a minimum number of clocks that guarantee detection ofthe pulse width by the host memory controller 6. In this way, in asingle request signal, the memory module controller 20 may signal arequest signal, such as a request to return data from the read buffer24, and one of a plurality of different functions.

Adjusting the Timing of Output from a First Memory Module Based onComponent Differences with a Second Memory Module to Match the Timingfrom the Second Memory Module

In certain implementations, the memory modules 8 a and 8 b may comprisedifferent types of memory modules that have different components. Forinstance, the memory module 8 a may or may not include registers anddata buffers not included in the memory module 8 b, and vice versa, andthe memory modules 8 a, 8 b may support different memory protocols.Described embodiments provide techniques for one memory module, such as8 b, to adjust its timing to match that of the other memory module,e.g., 8 a, so that the host memory controller 6 does not have to adjustfor different timings from different memory modules, such as differenttypes of DIMMs. By having the memory module controller 20 a, 20 b handlethe timing adjustments, excessive turnaround cycles and performance lossat the host memory controller is avoided.

FIG. 5 illustrates an embodiment of operations performed by the memorymodule controller 20, such as memory module controller 20 b, to adjustthe timing of output based on component differences with other memorymodules 8 a, 8 b on the bus 10. Upon initiating (at block 200) anoperation to output data from the data buffer 24, the memory modulecontroller 20 b determines (at block 202) a timing adjustment based onat least one component in at least one of the memory modules 8 a, 8 b onthe channel. Blocks 204-208 provide an embodiment of operations todetermine the timing adjustment. The memory module controller 20 b mayaccelerate (at block 204) the timing in response to the first memorymodule 8 b having at least one component effecting timing of the outputthat is not included in the other second memory module 8 a. Further, adelay may be added (at block 206) to the timing in response to the othersecond memory module 8 a on the bus 10 having at least one componenteffecting the timing of the output at the second memory module 8 b thatis not included in the first memory module 8 b.

The memory module controller 20 b may then determine (at block 208) anet timing adjustment from any added delay or acceleration of thetiming. The memory module controller 20 b adjusts (at block 210) atiming of output from the data buffer 24 to the host memory controller 6based on the determined timing adjustment to match a timing of output atthe second memory module 8 a.

For instance, if the memory module 8 b including the controller 8 bperforming the calculations includes a data buffer 24 not found in theother memory module 8 a, then the timing adjustment may compriseaccelerating the timing of the output when the other second memorymodule 8 a does not include a data buffer such as included in the firstmemory module 8 b. In another implementation, if the other memory module8 a has a register not included in the memory module 8 b performing thecalculation, such as the case with an RDIMM, then the timing adjustmentcomprises delaying the timing of the output to accommodate for theregister in the other memory module 8 a not included in the memorymodule 8 b doing the calculation. If the acceleration of timing for thedata buffer 24 was greater than the delay added for the register in theother memory module 8 a, then the net timing adjustment would comprisean acceleration of the timing. Likewise, if the delay added is greaterthan the acceleration, then the net adjustment would comprise adding adelay to the timing. If the memory module 8 b doing the calculationsdoes not include registers or data buffers 24 included in the othermemory module, such as if the other memory module 8 a is an RDIMM andLRDIMM, then the memory module controller 20 b may delay the timing toaccount for delays caused by the additional components in the othermemory module 8 a.

The memory modules 8 a, 8 b may have different types of components ontheir command, address and control busses to the bus 10 if they comprisedifferent types of DIMMs, such as UDIMMs, RDIMMs, and LRDIMMs.

In certain described embodiments, the output for which timing isadjusted comprises the output of data on a data bus in the bus 10 fromthe data buffer 24. In alternative embodiments, the output signalsadjusted may comprise output other than data output.

Although operations are described with respect to one memory moduleperforming timing adjustments, one or multiple memory modules 8 a, 8 bon the bus 10 may perform the timing adjustments of FIG. 5.

With the described timing adjustments, the memory module controller 20 bmay adjust the timing of its output, such as output from a data buffer24, to match the timing from the other memory module 8 a for similartypes of outputs so that the host memory controller 6 does not need toperform any of the timing adjustments to accommodate for the differentconfigurations of the different memory modules 8 a, 8 b on the bus 10.

Encoding Use of Registers in a Mode Register Set (MRS) Command

The memory module controller 20 may include mode registers 22. Incertain embodiments, the memory module controller 20 b may implement afirst protocol that is different than a second memory protocol used inother controller 8 a, such as DDR 4. However, the memory modulecontroller 20 b may support certain commands from the second protocol ofthe other memory module 8 a, such as DDR4, such as the Mode Register Set(MRS) command, yet use the command for a different purpose than used bythe memory module controller 20 a implementing the first memoryprotocol.

FIG. 6 illustrates an embodiment of the MRS command 250, which may ormay not include MRS fields from another memory protocol, such as DDR4.The command 250 specifies an operation code 252 indicating the MRSoperation. The address registers A0-A13 may be used to provide data forone of the mode registers 22 in the memory module controller 20 and theregister bits 254 indicate the mode register 22 to which to write thedata in addresses A0-A13. For instance, if there are 16 mode registers22, then four register bits 254, such as BA0, BA1, BG0, BG1, mayindicate one of the 16 mode registers 22 in the memory module controller20 to use.

In one embodiment, the MRS command 250 may comprise a single cyclecommand that may be used to provide configuration parameters to thememory module 8 before the bus 10 is trained for bus operations, such asread and write operations that may comprise two cycle commands. In thisway, the MRS command 250 uses address input signals A0-A17, shown in thepin-out design of FIG. 3 as line 52 and command input signals BG1:0 andBA1:0, shown as lines 54 and 56, respectively, in the pin-out design ofFIG. 3. In certain embodiments, address input signals A14-16 contain theMRS command operation code.

FIG. 7 illustrates an embodiment of operations performed by the hostmemory controller 6 and the memory module controller 20 to program moderegisters 22 in the memory module controller 20. During initialization,such as before the bus 10 is trained for read and operations, which maycomprise commands sent in two clocks, the host memory controller 6 maygenerate (at block 280) and send an MRS command 250 to indicate a moderegister 22 in the memory module controller 20 to configure with dataincluded in the address fields A13:0, which MRS command 250 may be senton one clock cycle.

The memory module controller 20 receives (at block 282) the MRS command250 and determines (at block 284) the mode register 22 indicated in theregister bits 254 on lines 34 and 35 (FIG. 3). The memory modulecontroller 20 then writes (at block 286) the data provided in theaddress bits A0:A13 into the determined mode register 22.

The host memory controller 6 may further use the MRS command 250according to the DDR4 protocol to send to a memory module, e.g., memorymodule 8 a, implementing the DDR4 protocol, to program one of eight moderegister on one of the memory chips 12 a, 14 a, 16 a, 18 a, where theregister bits BA0, BA1, BG0 identify the mode register in the memorychip and the bit BG1 indicates whether the bits are inverted. In thisway, the host memory controller 6 may use the same MRS command formatfor memory controllers 20 a, 20 b implementing different memoryprotocols to cause different operations according to the differentprotocols. For instance, when the MRS command 250 is used for a memorymodule 8 a supporting DDR4, the MRS command 250 writes data to a moderegister in one of the memory chips 12 a, 14 a, 16 a, 18 a. When usedfor a memory module 8 b having mode registers 22 in the memory modulecontroller 20, the MRS command 250 writes data to mode registers 22 inthe memory module controller 20 and not the DRAM chips 12, 14, 16, 18.In this way, the host memory controller 6 may use the same MRS commandformat with memory modules supporting different memory protocols, e.g.,DDR4 and some other protocol.

Accepting by a Memory Module a Second Half of a Command when a ChipSelect Signal is Only Received for a First Half of the Command

Described embodiments provide techniques for a memory module to accept acommand in multiple parts, such as in two halves, with only having toaccept one chip select signal for the memory module 8 so that the memorymodule 8 automatically accepts the second half of the command at a delayinterval from when the first half of the command was sent. Furtherembodiments provide techniques for incorporating a delay so as toautomatically accept the second half of the command in a high speedtiming mode, e.g., 2N timing, when the memory module 8 a, 8 b isoperating at higher speeds as opposed to a regular timing mode, e.g., 1Ntiming.

In certain embodiments, commands occupy two bits per lane and are senton back-to-back clocks. This allows the entire address to be sent in onecommand instead of two, such as sending row and column information inone command. The memory module controller 20 is made aware of the highspeed (2N) timing mode through the host memory controller 6 programmingthe mode registers 22 on the memory module controller 20.

FIG. 8 provides an embodiment of a timing chart for a regular timingmode, e.g., 1N timing, for commands, such as read commands, which aresent in two parts, shown as CMD0 a, CMD0 b, CMD1 a, CMD1 b, CMD2 a, CMD2b. The host memory controller 6 may put a first half of the command CMD0a and a chip select signal S0# 302, also shown as S0# line 58 in FIG. 3,on the bus on a clock cycle 300 for a first memory module 8 a. The firstmemory module 8 a may accept the first half of the command CMD0 a oncycle 300 upon receiving the chip select signal 302 and may furtherautomatically accept the second half of the command CMD0 b at a delayinterval from the first half of the command CMD0 a, such as one clockcycle later at clock cycle 304.

The host memory controller 6 may put a first half of the command CMD1 aand a chip select signal S2# 306, also shown as S2# line 60 in FIG. 3,on the bus on a clock cycle 308 to select a second memory module 8 b.The second memory module 8 b may accept the first half of the commandCMD1 a at cycle 308 upon receiving the chip select signal 306 and mayfurther automatically accept the second half of the command CMD1 b oneclock cycle later at cycle 310.

FIG. 9 provides an embodiment of a timing chart for a high speed timingmode for higher speeds than regular timing, e.g., 2N timing, where bothparts of each command, shown as CMD0 a, CMD0 b, CMD1 a, CMD1 b, CMD2 a,CMD2 b, remain on the bus 10 for two clock cycles. The host memorycontroller 6 may put a first half of the command CMD0 a on the bus on aclock cycle 320 for two cycles and place a chip select signal S0# 322,also shown as S0# line 38 in FIG. 3, on the bus on a clock cycle 324 forthe first memory module 8 a one cycle from when the first half of thecommand CMD0 a was placed on the bus 10, thus delaying the chip selectsignal in high speed timing mode. The first memory module 8 a may acceptthe first half of the command CMD0 a at the clock cycle 324 on receivingthe chip select signal 322 and may further automatically accept thesecond half of the command CMD0 b a delay interval, shown as two clockcycles from the chip select signal 322, at the beginning of clock cycle328.

The host memory controller 6 may put a first half of the command CMD1 aout on cycle 330 and a chip select signal S2# 332, also shown as S2#line 60 in FIG. 3, one cycle later on cycle 332 for a second memorymodule 8 b. The second memory module 8 b may accept the first half ofthe command CMD1 a on the clock cycle 336 of the chip select signal 332and may further automatically read the second half of the command CMD1 btwo clock cycles later at cycle 338. In this way, the host memorycontroller 6 delays the chip signal one clock cycle halfway through thefirst half of the command and the memory module controller 20 delaysreading the second half of the command two cycles after reading thefirst half of the command.

FIG. 10 illustrates an embodiment of operations performed by the hostmemory controller 6 and the memory module controller 20 for a 1N timingmode for commands occupying two bits on back-to-back cycles. The hostmemory controller 6 may program the memory module controller 20 throughbits in the mode registers 22 during initialization to operate in 1Ntiming mode. Upon initiating (at block 350) a two cycle command inregular timing mode, 1N, the host memory controller 6 places (at block352) a first half of a command (one cycle) on the bus 10 in a firstclock cycle. A chip select command is also placed (at block 354) on thebus 10 on the first clock cycle. Upon the memory module controller 20detecting (at block 356) the chip select signal directed to the specificmemory module 8 including the memory module controller 20 whenprogrammed in regular timing mode, the memory module controller 20accepts (at block 358) the first half of the command on the bus 10 onthe first clock cycle.

Further, the host memory controller 6 places (at block 360) a secondhalf of the command (on a back-to-back cycle from the first half) on thebus 10 in a second clock cycle one clock cycle from the first clockcycle. The memory module 8 selected by the chip select signal accepts(at block 362) the second half of the command on the bus 10 on thesecond clock cycle by waiting a one cycle delay from when the chipselect signal was received and the first half of the command accepted.The memory module controller 20 may automatically accept the second halfof the command on the bus 10 without requiring a chip select signal toaccess the bus 10.

FIG. 11 illustrates an embodiment of operations performed by the hostmemory controller 6 and the memory module controller 20 for a high speedtiming mode, e.g., 2N, for commands occupying two bits on back-to-backcycles. The memory module controller 20 may be programmed through bitsin the mode registers 22 during initialization to operate in high speedtiming mode. Upon initiating (at block 380) a two cycle command in highspeed timing mode, the host memory controller 6 places (at block 382) afirst half of a command (one cycle) on the bus 10 in a first clockcycle. A chip select signal is then placed (at block 384) on the bus 10on a second clock cycle which may be one clock cycle from the firstclock cycle. In this way, the chip select signal is placed on the bus ata delay, such as one clock cycle, from placing the first half of thecommand. Upon the memory module controller 20 detecting (at block 386)the chip select signal directed to the specific module 8 when programmedin high speed timing mode, the memory module controller 20 accepts (atblock 388) the first half of the command on the bus 10 on the secondclock cycle at a delay.

Further, the host memory controller 6 places (at block 390) a secondhalf of the command (two cycles from the first half) on the bus 10 in athird clock cycle two cycles from the first clock cycle. The memorymodule controller 20 in the memory module 8 selected by the chip selectsignal accepts (at block 392) accepts the second half of the command onthe bus 10 on a fourth clock cycle by waiting a two cycle delay fromwhen the chip select signal was received and the first half of thecommand accepted. The memory module controller 20 may automaticallyaccept the second half of the command without waiting for a chip selectsignal on the bus 10.

The described embodiments provide for the chip select signal to bedelayed by one clock signal in the high speed timing mode, e.g., 2Ntiming, from sending the first half of the command. Further, the memorymodule may automatically accept the second half of the command two clocksignals after the chip select signal. This delay in the chip selectsignal allows for additional setup time in high speed mode. The delayfor accepting the second half of the command allows for automaticacceptance of the command without requiring a chip select signal.

In alternative embodiments, the chip select signal may be placed on thebus and the second half of the command may be accepted at intervalsdifferent than the described one clock signal. Further, in alternativeembodiments, the commands may be comprised of more than two parts (e.g.,bits) and use more than two clock cycles and the memory module 8 a, 8 bmay automatically accept more than one additional part of the command atclock signal delay intervals from the chip select signal withoutrequiring additional chip select signals to accept.

Determining How to Set High Address Bits in a Memory Module

The memory module controller 20 may be configured to operate in memorymodules 8 having different pin and interface configurations, such as onememory module having more pins for addressing than another memory modulehaving fewer pins, such as an SO-DIMM. The memory module with feweraddressing pins may provide a smaller address space than a memory modulehaving more pins available for addressing. The supported interfaceconfiguration may vary due to the capabilities of the hot memorycontroller 6 and the bus 10 or vary due to the capabilities of the pinand interface configuration of the memory module 8, such as being anSO-DIMM or UDIMM.

For such embodiments, the memory module controller 20 may use one of themode registers 22 to indicate supported interface configurations, suchas indicating whether the memory module has pins available for highaddress bits or not. In such case, if the memory module controller 20 isoperating in a module 8 not having one or more pins for high addressbits available in other memory modules, then the memory modulecontroller 20 would use a predetermined value, such as zero, for thosehigh address bits unavailable in the module. In this way, the memorymodule controller 20 assumes a value of zero for the high address bitswhen there are no pins for receiving values for those high address bits.In one embodiment, the high address bits may comprise address bit A17 52and bit C2:0 62 shown in the pin-out diagram of FIG. 3. Certain memorymodules, such as an SO-DIMM, may not include pins 52 and 62.

FIG. 12 illustrates an embodiment of operations performed by the memorymodule controller 20 to configure settings for addressing. The hostmemory controller 6 may send an MRS signal to the memory module 8indicating the supported interface configuration. Upon receiving (atblock 400) the MRS signal indicating the supported interfaceconfiguration, the memory module controller 20 may update the moderegister 22 addressed by the MRS signal to indicate the supportedinterface configuration, which may indicate the DIMM type, e.g.,SO-DIMM, UDIMM, etc. or indicate what the interface supports, e.g., thatthe high address bits are supported or not. In response, the memorymodule controller 20 sets (at block 402) the addressed mode register 22indicating the interface configuration to indicate the communicatedinterface configuration, such as indicating whether high address bitsare supported or not.

FIG. 13 illustrates an embodiment of operations performed by the memorymodule controller 20 to handle addressing using the higher level addressbits. Upon receiving (at block 420) a command from the host memorycontroller 6 having address bits, the memory module controller 20determines the supported interface configuration from the mode register22, which information indicates whether the current memory module 8supports addressing at the high address bits. If (at block 422) thesupported interface configuration does not support high address bits,e.g., the memory module 8 does not have pins 52 and 62, then the atleast one high address bits for the received address are set to be apredetermined value, i.e., the high address bits are assumed to be zerowhen there are no pins for the high address bits. If (at block 422) thesupported interface configuration indicated in the mode register 22indicates high address bits are available, then the memory modulecontroller 20 uses (at block 426) the at least one high address bit forthe address received on the at least one high address pin 52, 62.

In alternative embodiments, the memory module controller 20 may supplypredetermined values for address bits other than the high address bitsnot having pins on the memory module.

The described embodiments allow a memory module controller to operatewithin memory modules having different pin configurations available foraddressing to provide high order address bits for a memory moduleconfiguration not having pins to provide high address bits. In this way,the memory module controller may be deployed and operate in memorymodules such as an SO-DIMM and UDIMM and provide the full addressingcapabilities for both interface configurations.

Providing Extended Operations for a CKE Low Signal

Described embodiments provide techniques to allow the pre-configurationof power management operations in a memory module 8 that are to beperformed at a later time when the memory module controller detects aclock enable (CKE) low signal on a CKE pin, such as the pins 64 or 66shown in the pin-out diagram of FIG. 3. This allows an extended seriesof power management operations to be performed upon activation of theCKE low signal, such as to enter a predefined sleep state.

Different possible sleep states could be activated upon receiving theCKE low signal depending on the previously sent pre-CKE command. Suchindicated states may comprise those specified in the AdvancedConfiguration and Power Interface (“ACPI”) Specification, such as an S3state of standby, sleep or suspend to the memory module 8, which remainspowered at a lower level, an S4 state of hibernation where the contentof the memory module 8 is saved to a non-volatile memory and the memorymodule 8 is powered-down, and an S5 state, where the memory module 8 ispowered-down while a minimum amount of power is supplied to the powersupply unit. The non-volatile memory to which content is saved, may comein various forms, including but not limited to NAND (flash) memory,ferroelectric random-access memory (FeTRAM), nanowire-based non-volatilememory, three-dimensional (3D) crosspoint memory such as phase changememory (PCM), memory that incorporates memristor technology,Magnetoresistive random-access memory (MRAM), Spin Transfer Torque(STT)-MRAM.

FIG. 14 illustrates an embodiment of operations performed by the hostmemory controller 6 and memory module controller 20 to facilitate powermanagement operations using the CKE low signal. To initiate operationsto change the power management mode, such as change to one of variousrecognized sleep modes, the host memory controller 6 sends (at block500) a pre-CKE command to the memory module controller 20 over the bus10 indicating one or more power management operations. In oneembodiment, the pre-CKE command may indicate one or more specificoperations or provide a code representing a series of operations. Forinstance, the pre-CKE command may indicate a power management state,such as a system state or sleep mode, e.g., S3, S4, and S5 of the ACPIsleep mode states, which the memory module controller 20 may interpretas the series of operations to perform to implement that state.

Upon receiving (at block 502) the pre-CKE command, the memory modulecontroller 20 sets the power management operation register 26 toindicate the at least one power management operation indicated in thepre-CKE command. At a subsequent time when the host memory controller 6wants the memory module 8 a, 8 b to implement the state change of theindicated power management operations, the host memory controller 6asserts (at block 506) the CKE low signal 56, e.g., low on pins 64 or 66(FIG. 2). Upon detecting (at block 508) the CKE low signal, the memorymodule controller 20 determines (at block 510) whether the powermanagement operation register 56 indicates operations to perform, suchas indicating a sleep mode state or specific operations. If nooperations are indicated, such as a null or default value, the memorymodule controller 20 may perform (at block 512) a default operation forhandling a CKE low signal, such as deactivating internal clock signals,a pre-charge power-down or self refresh operation. If operations or apower mode are indicated in the register 26, then the memory modulecontroller 20 performs (at block 514) the power management operationsindicated in the register 26 to implement a specified power managementstate, e.g., sleep state.

Described embodiments provide techniques for configuring a memory modulecontroller to perform a series of power management operations at asubsequent time using the CKE low signal. After the pre-CKE command issent, the host memory controller 6 will assert the CKE low signal totrigger more involved power management operations to change the powermode than would normally be triggered in response to the CKE low signal.With the described embodiments, fewer signals are needed for powermanagement because a more involved power management operation, such astransitioning to sleep mode, may be initiated with the CKE low signal

Providing a Host Memory Controller Write Credits for Write Commands

Described embodiments provide techniques to supply the host memorycontroller 6 write credits to use for sending write commands byincluding the write credits in returned read data packets to reduceconsuming bus bandwidth on the bus 10.

With respect to FIG. 1, the host memory controller 6 includes a writecredit counter 9 and will only send write commands when the write creditcounter 9 has positive credits. The write credit counter 9 isdecremented when sending a write command. There may be one write creditcounter 9 for each memory module 8 a, 8 b. The memory module 8 includesa write buffer 28 to buffer received write data that is then laterdestaged to storage elements in the memory chips 12, 14, 16, 18. Thememory module controller 20 has a write credit counter 30 indicatingaccumulated write credits to return to the host memory controller 6. Thewrite credits are used to regulate use of the write buffer 28 so thehost memory controller 6 does not send write data to overflow the writebuffer 28.

FIG. 15 illustrates an embodiment of operations for the host memorycontroller 6 and memory module controller 20 to process a write command.Upon generating a write command, the host memory controller 6 determines(at block 602) whether the write credit counter 30 is greater than zero,non-empty. If so, the write command is sent (at block 604) to the memorymodule 8. If (at block 602) the host write credit counter 9 is empty,then the host memory controller 6 waits until credits are available tosend the write command.

Upon receiving (at block 610) a write command, the memory modulecontroller 20 buffers (at block 612) the write data in the write buffer30. Upon destaging (at block 614) the write data from the write buffer30 to the storage elements in the memory chips 12, 14, 16, 18, thememory module controller 20 increments (at block 616) the write creditcounter 30 indicating a credit to return to the host memory controller 6to allow another write command. If (at block 618) the write creditcounter 30 exceeds a threshold, then the memory module controller 20generates (at block 620) a read data packet indicating no read data andindicating at least one of the write credits indicated in the writecredit counter 30. The read data packet is sent (at block 622) to thehost memory controller 6 and the write credit counter 30 is reduced (atblock 624) by the number of credits returned. In certain embodiments,there may be a limited number of credits returned, so the write creditcounter 30 may or may not be reduced to zero. In this way, if a readpacket is not sent for an extended time, the memory module controller 20sends a read data packet without data to provide write credits so thehost memory controller 8 is not starved of write credits and blockedfrom sending write commands. In alternative, the write credits may bereturned in packets other than a read data packet.

FIG. 16 illustrates an embodiment of operations performed by the memorymodule controller 20 to generate a read data packet to return to thehost memory controller 4. Upon generating (at block 640) a read datapacket including read data to return to a read request from host memorycontroller 6, if (at block 642) the write credit counter 30 is greaterthan zero, then the memory module controller 20 indicates (at block 644)in the read data packet some or all of write credits in the counter 30and sends (at block 646) the read data packet to the host memorycontroller 6. The write credit counter 30 is reduced (at block 648) bythe number of write credits returned, which may or may not be all thecredits in the counter 30. In this way, write credits are batched in theread data packet to return to the host memory controller 6, thusoptimizing message usage to communicate information. The memory modulecontroller 20 may not indicate all of the credits in one packet, asthere are a fixed set of responses. For instance, the memory modulecontroller 20 may be able to indicate 0, 1, or 4 in the read packet forthe number of write credits to return or 0, 1, 4, or 8 for the non-datapacket if write credits are being returned (at block 620 in FIG. 15)without read data.

FIG. 17 illustrates an embodiment of operations performed by the hostmemory controller 6 to process a read data packet from the memory module8. Upon receiving (at block 660) the read data packet, if (at block 662)the read data packet indicates write credits, then the host memorycontroller 6 increments (at block 664) the write credit counter 9 by thenumber of write credits indicated in read data packet. Afterincrementing the write credit counter 9 (from block 664) or if there areno provided write credits (from the no branch of block 662), if (atblock 666) the read data packet includes read data, the read data isprocessed (at block 670). The read data packet is discarded (at block668) after reading the data or if the packet does not include data (fromthe no branch of block 666)

Described embodiments provide techniques for the memory module 8 tocommunicate write credits to the host memory controller 6 in a mannerthat reduces bus 10 bandwidth by batching write credits in read packetsor other messages already being used.

Performing Error Handling Operations Using Error Signals

Described embodiments provide techniques for a simplified error flow atthe memory module 8 to coordinate error handling with the host memorycontroller 6. In described embodiments, the memory module controller 20may signal an error on the error pin 68 ERR0# shown in the pin-outdesign of FIG. 2. The memory module controller 20 may assert an error(ERR) low signal on the error pin 68 to signal commencement of errorhandling operations and assert an error (ERR) high signal on the errorpin 68 to signal that the error mode has ended and the bus 10 isreturned to an initial state ready for operation. In this waycommunication to coordinate error handling between the memory modulecontroller 20 and the host memory controller 6 on the bus 10 comprises alimited number of signals to avoid consuming bandwidth with moreextensive error handling coordination.

FIG. 18 illustrates an embodiment of operations between the memorymodule controller 20 and the host memory controller 6 to manager errorhandling operations upon an error being detected in the memory module 8.Upon detecting (at block 700) an error, the memory module controller 20asserts (at block 702) a first error signal, e.g., an ERR low signal onpin 68 (FIG. 2), on the bus 10 to signal to the host memory controller 6that error handling operations have commenced. Upon detecting (at block704) the first error signal, e.g., an ERR low signal on pin 68, the hostmemory controller 6 sends (at block 706) an acknowledgment that thefirst error signal was received and then continues to suspend (at block708) read and write operations to the memory module 8 having the errorin response to the first error signal. The host memory controller 6 mayperform further error handling operations, such as set (at block 710)the write credit counter 9 to a maximum value. In this way, the hostmemory controller 6 assumes that as part of error handling all writeswill be flushed from the write buffer 28 to storage elements in thememory chips 12, 14, 16, 18.

Upon receiving (at block 712) the acknowledgment from the host memorycontroller 6 of receiving the first error signal, the memory modulecontroller 20 performs error handling operations to return the bus 10 toan initial state. Such operations may include discarding (at block 716)all pending read requests, destaging (at block 718) writes in the writebuffer 28 to storage elements in the memory chips 12, 14, 16, 18, andclearing (at block 722) the write credit counter 30 of write credits toreturn. After completing error handling operations, the memory modulecontroller 20 asserts (at block 724) a second error signal, such as ERRhigh on error pin 68, to signal that error handling has completed. Upondetecting (at block 726) this second error signal, the host memorycontroller 6 resumes (at block 728) read and write operations to thememory module in response to detecting the second error signal.

With described embodiments, the memory module 8 and the host memorycontroller 6 coordinate with a limited number of signals and performfull error handling operations without exchanging numerouscommunications on the errors and transactions performed over the bus.Each component 8 and 20 assumes the other performs a fullre-initialization of the bus 10 in response to the error at the memorymodule 8.

Using an Error Signal to Indicate a Write Request Error and WriteRequest Acceptance

Described embodiments provide techniques for the memory modulecontroller 20 to indicate to the host memory controller 6 that a writerequest completed successfully by not asserting an error signal, such asan error signal low, within a predetermined time of the write requestbeing sent and indicating a write request failed by asserting an errorsignal. Upon detecting the error signal, the host memory controller 6resends the write request if the error signal is received within apredetermined time of sending the write request. In this way, bus 10bandwidth is conserved by not sending write complete acknowledgements tothe host memory controller 6 after completing every write request.

FIG. 19 illustrates an embodiment of operations performed by the memorymodule controller 20 and a host memory controller 6 to indicateacceptance of a write request and errors in a write request. Upon thememory module controller 20 detecting (at block 750) a write error withone of the write requests being processed, the memory module controller20 asserts an error signal, such as an error low signal ERR0# on pin 68(FIG. 3). The memory module controller 20 keeps the error high signalactive to indicate no error has occurred. The memory module controller20 may additionally use the ERR0# signal on pin 68 to indicate errorsunrelated to write request errors. Further, the memory module controller20 impliedly indicates successful completion of a write request by notsending the error low signal within a predetermined time of the writerequest, such as when the write request was sent or received.

Upon the host memory controller 6 detecting (at block 754) the error lowsignal, if (at block 756) the error low signal is received within apredetermined time of one or more write requests, then the host memorycontroller 20 resends (at block 758) the determined one or more requestssent within the predetermined time of receiving the error low signal. Incertain embodiments, the host memory controller 20 resends the writerequests even if the error signal is unrelated to write errors. In thisway, the host memory controller 20 processes write requests as havingcompleted successfully if the error signal low is not received withinthe predetermined time and processes the write request as having failedif the error signal low is received within the predetermined time evenif the error signal low was signaling an error unrelated to writerequest errors.

After resending the write requests (at block 758) or if there are writerequests sent within the predetermined time (from the no branch of block756), the host memory controller 6 determines (at block 760) whetherthere is an error handling operation related to the error low signal toperform unrelated to write errors. If so, then the host memorycontroller 6 performs (at block 762) the error handling operationunrelated to write errors.

With the described embodiments, the memory module 8 does not send writecomplete acknowledgments after completing every write. Instead, the hostmemory controller 6 assumes the write completed if an error signal isnot received within a predetermined time following the write request.Further, the host memory controller 6 resends the write request if theerror signal is received within the predetermined time of sending thewrite request even if the memory module controller 20 was signaling anerror unrelated to a write error.

Scrambling Read Data in a Memory Module

Described embodiments provide techniques for the memory modulecontroller 20 to descramble write data and store the write dataunscrambled and then scramble the stored data to return to a readrequest, including the scrambling of the read address. Scrambling thedata being transmitted on the bus 10 for both read and writes isperformed to avoid the probability of a vexatious sequence occurring inthe transmission that would cause errors on the bus 10.

To allow for the scrambling of the read data, the host memory controller6 and the memory module controller 20 maintain scramble seed values 11and 32 (shown in FIGS. 1 and 2), respectively. Both seed values areinitialized to a common value, and then incremented after processing aread data packet so that the incremented seed values 32 and 11 areindependently set to the same value for the same read data packet andare used to scramble and descramble read requested data in a read datapacket returned to the host memory controller 6 in response to a readrequest. Further, the memory module controller 20 and the host memorycontroller 6 implement circuit logic for the same data scramblingalgorithm using the seed values 11, 32 to scramble and descramble datato remove the likelihood of a vexatious sequence occurring on the bus10. In alternative embodiments, the host memory controller 6 and thememory module controller 20 may update the seed values 11 and 32 byadditional operations known in the art.

FIG. 20 illustrates an embodiment of operations performed by the memorymodule controller 20 and a host memory controller 6 to scramble readdata transmitted across the bus 10. Upon receiving (at block 800) a readrequest for a read address from the host memory controller 6, the memorymodule controller 20 retrieves (at block 802) the unscrambled read datafrom a storage element, e.g., DRAM chip 12, 14, 16, 18, in the memorymodule 8. The memory module controller 20 uses (at block 804) thescramble seed 32 to scramble the requested read data and the readaddress to include in a read data packet to return (at block 806) to theread request from the host memory controller 6. The scrambler seed 32 isthen updated (at block 808). In one embodiment, then scrambler seed 11,32 is updated in a pseudo-random fashion using a linear feedback shiftregister (LFSR) circuit.

Upon receiving a read packet, the host memory controller 6 uses (atblock 812) the scrambler seed 11 to descramble the read data packet todetermine the read data and read address. The read request associatedwith the unscrambled address is then determined (at block 814) so thatthe read data may be returned to that read request. The scrambler seed11 is updated (at block 816). In an alternative embodiment, thescrambler seeds 11 and 32 may be updated before being used to scrambleand descramble.

FIG. 21 illustrates an embodiment of operations performed by the memorymodule controller 20 to manage scrambled write data. Upon receiving (atblock 830) a write request having scrambled write data from the hostmemory controller 6, the memory module controller 20 descrambles (atblock 832) the scrambled write data using the write address of the writerequest and then writes (at block 834) the unscrambled data to thememory chip 12, 14, 16, 18 in the memory module 8.

Described embodiments allow the memory module controller 20 to store theread data unscrambled and then scramble both the read data and addressto return on the bus 10 by using seed values 11 and 32 that eachcomponent 8 and 20 updates for scrambling and descrambling operations.

Selecting One of a Plurality of Bus Interface Configurations to Use

Described embodiments provide an interface parameter 34 to configure inthe memory module 8 that is used by the memory controller 20 todetermine the bus interface configuration used by the memory module 8.In this way, the memory module controller 20 may operate with differentbus interfaces 10, such as bus interfaces having different bus widths,i.e., bus data widths, such as 9 bit interface, 18 bit interface, 72 bitinterface, etc. For instance, different types of DIMMs in which thememory module controller 20 may be implemented may have different buswidth configurations, such as different numbers of pins, e.g., 72, 168,184, 240, etc., to implement the different bus widths.

FIG. 22 illustrates an embodiment of operations performed by the memorymodule controller 20 to determine (at block 900) the interface parameter34. The memory module controller 20 may determine the bus 10 interfaceconfiguration during initialization by scanning the bus 10 or byquerying the host memory controller 6. Alternatively, the host memorycontroller 6 or other component may communicate information on the bus10 interface configuration, such as the bus width, pin configuration,etc., over the bus 10 during initialization. In a yet furtherembodiment, the memory module 8 may have one or more strapping pinsexternal to the bus 10 that are coupled to the memory module 8 thatcommunicate the bus 10 interface configuration. The host memorycontroller 6 or other component may assert the bus interfaceconfiguration on the at least one strapping pin. One strapping pin maybe used if there are only two supported bus interface configurations tocommunicate. If there are more than two supported bus interfaceconfigurations that the memory module controller 20 supports, then theremay be additional pins to indicate more than two bus interfaceconfigurations. Upon determining (at block 900) the bus interfaceconfiguration, the interface parameter 32 is set to indicate thedetermined interface parameter.

FIG. 23 illustrates an embodiment of operations performed by the memorymodule controller 20 to process a transfer request based on the businterface configuration. Upon initiating an operation to process atransfer request (at block 930), the memory module controller 20 selects(at block 932) a bus interface configuration corresponding to theinterface parameter 32, where the selected bus configuration maycomprise one of a first, second, third, or further bus configurations,each having a different bus width and pin configuration. For instance,the bus configurations may comprise a 9 bit, 18 bit, and 72 bit databus, where each of these bus configurations may have a different numberpins. This selected bus configuration is used when processing transferrequests and other operations.

The memory module controller 20 generates (at block 934) a number oftransfers to process the transfer request based on the bus width of theselected bus interface configuration. For instance, if the selected busconfiguration has a smaller bus width than other possible configurationssupported by the memory module controller 20, then that busconfiguration will require more transfers to accommodate its smaller buswidth than required for a supported bus interface configuration having alarger bus width and more pins. In this way, the memory modulecontroller 20 may divide a transfer request into different number of bustransactions based on the bus width of the selected bus interfaceconfiguration. The generated transfers are transmitted (at block 936) onthe selected bus interface configuration.

Described embodiments provide a memory module controller 20 that isoperable in memory modules 8 having different bus interfaceconfigurations to allow the memory module controller 20 to support thebus configuration of the memory module 8 in which it is implemented.

It should be appreciated that reference throughout this specification to“one embodiment” or “an embodiment” means that a particular feature,structure or characteristic described in connection with the embodimentis included in at least one embodiment of the present invention.Therefore, it is emphasized and should be appreciated that two or morereferences to “an embodiment” or “one embodiment” or “an alternativeembodiment” in various portions of this specification are notnecessarily all referring to the same embodiment. Furthermore, theparticular features, structures or characteristics may be combined assuitable in one or more embodiments of the invention.

Similarly, it should be appreciated that in the foregoing description ofembodiments of the invention, various features are sometimes groupedtogether in a single embodiment, figure, or description thereof for thepurpose of streamlining the disclosure aiding in the understanding ofone or more of the various inventive aspects. This method of disclosure,however, is not to be interpreted as reflecting an intention that theclaimed subject matter requires more features than are expressly recitedin each claim. Rather, as the following claims reflect, inventiveaspects lie in less than all features of a single foregoing disclosedembodiment. Thus, the claims following the detailed description arehereby expressly incorporated into this detailed description.

1. An apparatus in communication with a host memory controller over abus, comprising: a scrambler seed; memory module controller logic to:retrieve data stored in a storage element of a memory module in responseto a read request; use the scrambler seed to scramble the retrieved dataproduce scrambled data to include in a read data packet; return the readdata packet having the scrambled data to the host memory controller; andupdate the scrambler seed.
 2. The apparatus of claim 1, wherein thescrambler seed scrambles an address of the retrieved data included inthe read data packet.
 3. The apparatus of claim 1, wherein the update ofthe scrambler seed updates the scrambler seed in a pseudo-randomfashion.
 4. The apparatus of claim 1, wherein the memory modulecontroller logic is further to use a scrambler algorithm to scramble theretrieved data, wherein the scramble algorithm comprises a samescrambler/descrambler algorithm implemented at the host memorycontroller to scramble/descramble the scrambled read data in the readdata packet.
 5. The apparatus of claim 1, wherein the memory modulecontroller logic is further to: receive a write request having scrambledwrite data indicating a write address in the memory module; descramblethe scrambled write data using the write address to produce unscrambledwrite data; and store the unscrambled write data at the write address inthe memory module.
 6. An apparatus in communication with a memory moduleover a bus, comprising: a scrambler seed; host memory controller logicto: receive a read data packet having scrambled read data returned inresponse to a read request; update the scrambler seed in response toreceiving the read data packet; and use the scrambler seed to descramblethe scrambled data.
 7. The apparatus of claim 6, wherein a scrambledaddress of the scrambled read data is in the read data packet, whereindescrambling the scrambled read data further comprise descrambling thescrambled address to determine the read request for which the read datapacket is returned.
 8. The apparatus of claim 7, wherein the update tothe scrambler seed updates the scrambler seed in a pseudo-randomfashion.
 9. The apparatus of claim 6, wherein the host memory controllerlogic is further to use a scrambler algorithm to descramble thescrambled read data, wherein the scramble algorithm comprises a samescrambler/descrambler algorithm implemented at the memory module toscramble read data in the read data packet.
 10. A method, comprising:retrieving data stored in a storage element of a memory module inresponse to a read request; using a scrambler seed to scramble theretrieved data to produce scrambled data to include in a read datapacket; returning the read data packet having the scrambled data to ahost memory controller; and updating the scrambler seed.
 11. The methodof claim 10, wherein the scrambler seed scrambles an address of theretrieved data included in the read data packet.
 12. The method of claim10, wherein updating the scrambler seed comprises updating the scramblerseed in a pseudo-random fashion.
 13. The method of claim 10, furthercomprising: using a scrambler algorithm to scramble the retrieved data,wherein the scramble algorithm comprises a same scrambler/descrambleralgorithm implemented at the host memory controller toscramble/descramble the scrambled data in the read data packet.
 14. Themethod of claim 10, further comprising: receiving a write request havingscrambled write data indicating a write address in the memory module;descrambling the scrambled write data using the write address to produceunscrambled write data; and storing the unscrambled write data at thewrite address in the memory module.
 15. A method, comprising: receivinga read data packet having scrambled read data returned in response to aread request; updating a scrambler seed in response to receiving theread data packet; and using the scrambler seed to descramble thescrambled read data.
 16. The method of claim 15, wherein a scrambledaddress of the scrambled read data is in the read data packet, whereindescrambling the scrambled read data further comprise descrambling thescrambled address to determine the read request for which the read datapacket is returned.
 17. The method of claim 16, wherein updating thescrambler seed comprises updating the scrambler seed in a pseudo-randomfashion.
 18. The method of claim 15, further comprising: using ascrambler algorithm to descramble the scrambled read data, wherein thescramble algorithm comprises a same scrambler/descrambler algorithmimplemented at a memory module to scramble read data in the read datapacket.